As one might imagine, designing a computer chip is a painstaking and intricate process. Creating the blueprint for a chip that comprises multiple layers of complex circuitry involves the creation of schematic diagrams to map electrical circuits, floor planning to manage where each component fits, and routing connections between those components — not to mention a rigorous process of simulation, testing, and refining before the chip is ready to move on to fabrication. Designing one chip requires teams of engineers and a significant financial and time investment.

Computer chip counterfeiters have found a shortcut. By taking existing chips, opening them up and separating the individual layers, they can take a top-down view and use image-processing tools to stitch the layers back together to effectively reverse engineer the original design. As NYU Abu Dhabi Assistant Professor of Engineering Ozgur Sinanoglu explained, this illegal practice has significant economic, security, and reliability implications. In addition to the potential to reveal insights into critical security applications, the theft and cloning of chips affect companies and individuals whose livelihood depends on this intellectual property.

Sinanoglu and the members of his Design-for-Excellence lab at NYUAD have received recognition, and a USD 500,000 grant from the US National Science Foundation, for their work on developing and advancing techniques to build protections — against intellectual property, reliability, and security-related threats — directly into the chip-design process.

In the case of reverse engineering, Sinanoglu is investigating ways to optimize the use of camouflaged gates with dummy connections (created by external casing with no wiring) to disguise the actual functionality of individual components.

"Normally if a component has a certain function, it looks a certain way," he explained. "By designing what looks like a union of two different components from a top-down view, even though in reality it is still only performing one function, it creates ambiguity for reverse engineers trying to analyze the images; they are not able to figure out what the component does."

While designs for camouflage gates are available from select companies in the industry, it is still a nascent technique lacking a structured methodology and approach to make decisions about how and where to effectively use them on a chip to provide a sufficient level of security. Another problem: camouflaged components cannot be used freely in the design due to cost considerations. Being bigger, they consume more space and power, creating an optimization problem.

Sinanoglu, together with members of the NYU Polytechnic School of Engineering — doctoral student Jeyavijayan Rajendran, undergraduate Michael Sam, and Professor of Electrical and Computer Engineering Ramesh Karri — have analyzed the connections and functionality of individual components on a chip to create an algorithm. It provides a theoretical solution to identify chips that can most effectively camouflage in order to meet a certain level of security while controlling the cost. Findings were published in the paper "Security Analysis of Integrated Circuit Camouflaging," which won the Best Student Paper recognition from among 530 submissions at the 2013 Association for Computing Machinery Conference on Computer and Communications Security, one of the world's top computer security conferences.